Charge pump circuits provide for generating a voltage (known as boost voltage) greater than the supply voltage, for catering to the requirements of certain applications. For example, present nonvolatile flash memories at times present a particularly low supply voltage, as low as 3 V, whereas a higher gate voltage is required for reading the cells.
For this purpose, charge pump circuits are based on the principle of alternating two phases, the first of which comprises charging a capacitor, and the second of which comprises pulling up one terminal of the capacitor and connecting the other terminal to an output via controlled switches, to achieve an output voltage greater than supply.
U.S. Pat. 5,191,232, filed by Silicon Storage Technology, relates to a voltage boost circuit (charge pump) for EEPROM memories, comprising a number of cascade-connected stages of the above type, each of which increases the voltage generated in the previous stage, so that the output voltage of the circuit, roughly speaking, equals the supply voltage multiplied by the number of stages. The stages are so timed that each at a given phase is followed by another at the opposite phase, which timing is achieved by means of a number of inverters, one for each stage of the charge pump, cascade-connected in a loop so that the output of the last inverter is connected to the input of the first.
As stated, the above described charge pump provides for boosting the input voltage (supply) when a high input to output voltage ratio is required. However, such a charge pump is unsuitable for applications requiring a lower ratio (e.g., an output voltage equal to twice the input voltage) but high power. In fact, for achieving a low boost: ratio, a correspondingly small number of stages must be provided, only one of which is connected directly to the output line. In this case, a very high oscillation frequency, due to the propagation time of the timing pulse in the inverter loop, would be produced. This very high oscillation frequency prevents full charging of the capacitor. Such a situation would in fact result in conflicting requirements: on the one hand, high power capacitors are required for high power charge transfer; on the other, an increase in the capacitance of the capacitors results in a reduction in the charge of the capacitors at each cycle and hence in output power.
Moreover, the efficiency of the known circuit is extremely poor in the presence of low supply voltages, e.g., 3 V. The capacitor of the known circuit, in fact, can only be charged to the input value less the threshold voltage of the diode interposed between the capacitor itself and the previous stage; and, similarly, fails to transfer the full charge, due to the voltage drop of the diode between itself and the next stage (or output).